Region 1

Sail to Alaska with IEEE-USA! IEEE-USA's cruising saga continues in 2024 to the magnificent, wild Alaskan frontier. Building off of the success of IEEE-USA’s 50th Anniversary Cruise, IEEE-USA will be hosting a 7-night Alaska Cruise 9-16 September 2024. We’ll be cruising in style aboard Royal Caribbean’s Quantum of the Seas from Seattle to stops in Sitka, Skagway, Juneau, and Victoria, BC, before concluding our cruise back in Seattle. Please remember that to participate in the IEEE-USA Alaska Cruise activities, you must book through the (https://cruise.ieeeusa.org). Details: (https://cruise.ieeeusa.org/) Bldg: Smith Cove Cruise Terminal at Pier 91, Port of Seattle, 2001 West Garfield Street, Seattle, Washington, United States, 98119

This course has been canceled! Course: 4 weeks, 1 class weekly, evening. Rates are listed below. September 16, 23, 30 and October 7, 2024.We can offer Continuing Education Units (CEU) and Professional Development Hours (PDH), if requested. A small fee may apply for the credits. Course Overview: Field-programmable gate arrays (FPGAs) are versatile integrated circuits that offer a flexible and reconfigurable hardware platform for implementing custom digital circuits, particularly in applications requiring specialized architectures. Unlike application-specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacturing using hardware description languages (HDLs), enabling rapid prototyping and iterative design processes. FPGAs can be found in telecommunications, signal processing, aerospace, and other scenarios demanding high-performance computing, parallel processing, low-latency data processing, and real-time operations. The newest trends include integrating FPGAs with systems on chip (SoCs) for implementing low-latency machine learning (ML) and artificial intelligence. This Advanced Digital Design course is an intensive program designed to build upon foundational concepts in digital logic design and equip students with the skills needed to implement robust high-speed ML algorithms on an FPGA. Through a combination of theoretical lectures, hands-on exercises, and practical projects, students will explore advanced FPGA topics encompassing architectural considerations, signal integrity, timing analysis, and optimization techniques to achieve reliable and efficient high-speed designs. Additionally, this course will encourage students to explore current research papers and real-world industry applications to foster a deeper appreciation for advancements in state-of-the-art FPGA design. Target audience: Students and professionals with a base knowledge of FPGA design looking to advance hardware design skills for developing complex customized circuits for efficient implementation of ML. Benefits of attending: - Valuable professional development creating skills that lead to job offers - Reinforce and expand knowledge of VHDL and FPGA-specific design methodology. - Develop skills for implementing high-speed, robust, reliable circuits on FPGAs. - Gain understanding of real-world industry applications of FPGAs and SoCs. Course Objectives: By the end of this course, students will possess the expertise needed to tackle complex high-speed hardware design challenges using FPGAs. They will be well-prepared to contribute to cutting-edge research, industry projects, and advancements in areas such as telecommunications, data centers, embedded systems, and high-performance computing. Prerequisites: - Understanding of digital logic design principles and methodology (e.g., Boolean algebra, finite state machines, data path elements) - Familiarity with VHDL programming (or Verilog) - Experience with FPGA development boards and tools (e.g., Vivado) Detailed Course Outline: - Review of Digital Logic Design and FPGA Programming - Boolean algebra, combinational and sequential circuits, finite state machines - FPGA, SoC, and SoM architectures and toolchains - VHDL programming techniques and design methodology - Writing effective testbenches, RTL simulation in Vivado - Introduction to ML algorithms and FPGA-specific optimization strategies - High-throughput Communication on FPGAs - Pipelining and parallelism for high-speed designs - Synchronous vs. asynchronous communication protocols (SPI, SCI, UART, LVDS, I2C, PCIe, USB, Ethernet, etc.) - Compare hardware/software/firmware implementations of ML: throughput speeds, resource utilization, and latency - Methods used to achieve ultra-high sampling rates (>> system clock, GS/s range) - Utilizing advanced IP cores and IO buffers for high-speed interfaces and data storage - Advanced FPGA Techniques for High-speed Systems - Clock domain crossing verification and synchronization techniques - Resource utilization, critical path identification, and optimization strategies - Timing constraints, static and dynamic timing analysis - Signal integrity analysis - High-Speed Design Verification and Testing - Simulation-based verification techniques, advanced debugging, and waveform analysis - Post-layout verification and back-annotation - Test and validation strategies for high-speed designs - Utilizing debug cores for real-time logic analysis - Machine Learning on FPGAs - Algorithm validation and verification in software - Compare capabilities and implementation strategies of ML on FPGAs, SoCs, and SoMs - Optimization strategies for efficient ML implementation in hardware (e.g., convolution) - Digital Systems in Industry - Techniques and best practices for scalable, reusable, reliable, and robust FPGA design - Board-level considerations for high-speed signals: PCB layout guidelines, power distribution and decoupling, transmission line theory and termination techniques - Emerging trends for FPGA-based digital signal processing (DSP) applications ________________________________________________________________________________________________ Speaker(s): Kendall Farnham, PhD, Room: 2C130, Bldg: Center, MITRE Corporation and On-Line, 202 Burlington Road, Bedford , Massachusetts, United States, Virtual: https://events.vtools.ieee.org/m/371709

September 2024 LI Section ExCom Meeting Welcome Back - Excom Members Agenda: Call to Order Chair’s Report (Rhonda Green) Vice Chair’s Report (James Martino) Secretary’s Report (Udit Sharma) Treasurer's Report (Sandy Mazzola) Society Reports (Chapter Chair & Vice Chair) Affinity Group Reports (Group Chair & Vice Chair) Committee Reports (Committee Chair, Vice Chair) New Business & Voting Items (All) Action Items (Secretary, All) Closing Remarks and Adjourn (Rhonda Green) Room: Feynman Conference Room, Zebra Technologies, One Zebra Plaza, Holtsville, New York, United States, 11742, Virtual: https://events.vtools.ieee.org/m/434046