Artificial Intelligence (AI) accelerator designs for the edge devices have attracted vast interest, where accelerating Deep Neural Network (DNN) using Processing-in-Memory (PIM) and Processing-in Sensor (PIS) platforms is an actively-explored direction with great potential. Such accelerators, which simultaneously aim to address power- and memory-wall bottlenecks, have shown orders of performance enhancement in comparison to the conventional computing platforms with Von-Neumann architecture. As one direction of accelerating DNN in PIM/PIS, resistive memory array (aka. crossbar) has drawn great research interest owing to its analog current mode weighted summation operation which intrinsically matches the dominant Multiplication-and-Accumulation (MAC) operation in DNN, making it one of the most promising candidates. An alternative direction is through bulk bit-wise logic operations directly performed on the content in digital memories.
The main goal of this seasonal school is to dive deep into the rapidly developing field of PIM and PIS with a focus on the intelligent memory and sensor circuit and system at the edge and cover its cross-layer design challenges from device to algorithms. The Second IEEE Seasonal School in Circuits and Systems on Intelligent Memory & Sensor at the Edge (IMS 2023) offers tutorial level talks by leading researchers from multiple disciplines and prominent universities and promotes student participation to demonstrate new research and results, discuss the potential and challenges of the edge accelerators, future research needs, and directions, and shape collaborations.
Date: 10 Oct 2023
- Time: 09:30 AM to 01:00 PM
- All times are (UTC-05:00) Eastern Time (US & Canada)
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154 Summit Street, Newark, NJ 07102
Newark, New Jersey
Building: Central King Building
Room Number: 116Click here for Map
Dr. Ajay K. Poddar, Email:firstname.lastname@example.org
Dr. Edip Niver, email: email@example.com
Dr. Durga Misra, Email: firstname.lastname@example.org
Dr. Anisha M. Apte, Email: email@example.com
- Co-sponsored by IEEE North Jersey Section
Topic: Brain-inspired Electronics
I will share my vision and enthusiasm for the growing fields of brain-inspired computing and robotics. The focus of my presentation will be on metal-insulator transitions in quantum materials such as correlated perovskite semiconductors that can be used to emulate the characteristics of neurons and synapses in the brain and serve as building blocks for AI hardware. We will then discuss how features of intelligence noted in various insects, mammals and birds by biologists can be implemented in electronic devices and circuits for learning and decision-making. Creation of neural links between brains of live mice and electronics will be then presented.
Biography: Dr. Ramanathan received his Ph.D. from Stanford University and was a research staff member at Components Research Labs at Intel for over three years. He then served on the applied physics faculty at Harvard University for nearly a decade. Their group conducts research in oxide semiconductors for neuromorphic computing, optoelectronics and haptic intelligence, and collaborates with a broad set of research groups across engineering and natural sciences. Ramanathan has a strong record of securing external funding from the U.S. Department of Defense and from the National Science Foundation, publishing more than 195 peer-reviewed articles in major research journals. He has delivered numerous invited talks and plenary addresses at international conferences, and has been invited to attend workshops organized by the United States National Academy of Sciences Keck Futures Program and the U.S. National Academy of Engineering Frontiers of Engineering Symposium and has served as a Kavli Fellow Lecturer for the U.S. National Academy of Sciences. Email: firstname.lastname@example.org
Topic: Cross-layer Design Optimization for Processing-in-Memory AI Systems
The applications of state-of-the-art AI algorithms have been extended to many exciting domains, such as natural language processing, recommendation systems, edge sensing etc. Processing-in-memory (PIM) computing paradigm is emerging as a promising candidate for AI system implementations that pursue low memory access cost and high computational throughput. PIM-based AI systems not only require dedicated power-efficient circuits, but also benefit from fine-grained architecture-algorithm optimizations. In this talk, I will introduce our latest research about cross-layer design optimization methodologies for PIM-based AI systems. These works offer full-stack solutions to resolve power and throughput bottlenecks of AI systems based on circuit-architecture-algorithm co-design.
Biography: Dr. Hai “Helen” Li is the Clare Boothe Luce Professor and Department Chair of the Electrical and Computer Engineering Department at Duke University. She received her B.S. and M.S. from Tsinghua University and her Ph.D. from Purdue University. Her research interests include neuromorphic circuits and systems for brain-inspired computing, machine learning acceleration and trustworthy AI, conventional and emerging memory design and architecture, and software and hardware co-design. Dr. Li served/serves as the Associate Editor for multiple IEEE and ACM journals. She was the General Chair or Technical Program Chair of numerous IEEE/ACM conferences and the Technical Program Committee members of over 30 international conference series. Dr. Li is a Distinguished Lecturer of the IEEE CAS Society (2018-2019) and a Distinguished Speaker of ACM (2017-2020). Dr. Li is a recipient of the NSF Career Award, DARPA Young Faculty Award, TUM-IAS Hans Fischer Fellowship from Germany, ELATE Fellowship, nine best paper awards and another nine best paper nominations. Dr. Li is a fellow of ACM and IEEE. Email: email@example.com
Event Time: 9:30 AM to 1:00 PM
Central King Building (CKB), Room 116, NJIT, Newark
- 9:30 AM – 10:00 AM Breakfast, Coffee, Registration and Networking
- 10:00 AM – 10:10 AM Welcome and Opening Remarks by Dr. Misra, Chair CASS/EDS Chapter, Professor and Chair ECE Dept
- 10:10 AM – 11:00 AM Talk by Dr. Shriram Ramanathan (Rutgers, The State University of New Jersey), Professor and Rodkin-Weintraub Chair in Engineering: Brain-inspired Electronics
- 11:00 AM – 11:50 AM Talk by Dr. Hai “Helen” Li (Duke University), Clare Boothe Luce Professor and Chair of Electrical and Computer Engineering: Cross-layer Design Optimization for Processing-in-Memory AI Systems
- 11:50 AM – 12:10 PM Networking & Discussion
- 12:10 PM – 1:00 PM Lunch & Concluding Remarks by Prof. Shaahin Angizi, Vice-Chair, IEEE CAS/ED Chapter
Seminar is in CKB 116. All Welcome: There is no fee/charge for attending IEEE technical seminar. You don’t have to be an IEEE Member to attend. Refreshmenta and lunch are free for all attendees. Please invite your friends and colleagues to take advantage of this Invited Distinguished Lecture. REGISTRATION is REQUIRED